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LIS2L02AQ
INERTIAL SENSOR: 2Axis - 2g/6g LINEAR ACCELEROMETER
PRODUCT PREVIEW
s s s
s s s
3V TO 5.25V SINGLE SUPPLY OPERATION THE SENSITIVITY IS ADJUSTED WITH A TOTAL ACCURACY OF 10% THE OUTPUT VOLTAGE, OFFSET, SENSITIVITY AND TEST VOLTAGE ARE RATIOMETRIC TO THE SUPPLY VOLTAGE DEVICE SENSITIVITY IS ON-CHIP FACTORY TRIMMED EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY
QFN-44 ORDERING NUMBER: LIS2L02AQ
DESCRIPTION The LIS2L02AQ is a dual-axis linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide an analog signal to the external world. The sensing element, capable to detect the acceleration, is manufactured using a dedicated process called THELMA (Thick Epi-Poly Layer for Microactuators and Accelerometers) developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS2L02AQ has a user selectable full scale of 2g, 6g and it is capable of measuring accelerations BLOCK DIAGRAM
over a maximum bandwidth of 4.0 KHz for both the X and Y axis. The device bandwidth may be reduced by using external capacitances. A self-test capability allows the user to check the functioning of the system. The LIS2L02AQ is available in plastic SMD package and it is specified over a temperature range extending from -40C to +85C. The LIS2L02AQ belongs to a family of products suitable for a variety of applications: - Antitheft systems - Inertial navigation - Virtual reality input devices - Vibration Monitoring, recording and compensation - Appliance control - Robotics
Routx S1X S1Y CHARGE AMPLIFIER S/H
Voutx
rot
S2Y S2X
MUX
DEMUX
Routy S/H
Vouty
VOLTAGE & CURRENT REFERENCE
TRIMMING CIRCUIT & TEST INTERFACE
CLOCK & PHASE GENERATOR
December 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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PIN DESCRIPTION
N 1 to 3 4 5 6 7 8 9-13 14 15 16 17-18 19 20 21 22-23 24-25 26 27 28 29-44 Pin NC GND Vdd Vouty ST Voutx NC PD NC FS Reserved NC Reserved NC Reserved NC Reserved Reserved Reserved NC Internally not connected 0V supply Power supply Output Voltage Self Test (Logic 0: normal mode; Logic 1: Self-test) Output Voltage Internally not connected Power Down (Logic 0: normal mode; Logic 1: Power-Down mode) Internally not connected Full Scale selection (Logic 0: 2g Full-scale; Logic 1: 6g Full-scale) Leave unconnected Internally not connected Leave unconnected Internally not connected Leave unconnected Internally not connected Connect to Vdd or GND Leave unconnected or connect to Vdd Leave unconnected or connect to GND Internally not connected Function
PIN CONNECTION (Top view)
NC NC NC NC NC NC NC NC NC NC NC
1
Y
NC NC NC GND NC NC NC NC NC
X
Vdd Vouty ST Voutx
LIS2L02AQ
Reserved Reserved Reserved NC NC Reserved
DIRECTION OF THE DETECTABLE ACCELERATIONS
NC NC NC
NC
NC
PD
NC
Reserved
Reserved
Reserved
Reserved
NC
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Reserved
FS
LIS2L02AQ
ELECTRICAL CHARACTERISTCS (Temperature range -40C to +85C)
Symbol Vdd Idd Voff Ar Parameter Supply voltage Supply current Zero-g level Acceleration range Tamb = 25C ratiometric to Vdd 0V on FS pin Vdd on FS pin So Sensitivity ratiometric to Vdd Tamb = 25C Full-scale = 2g Tamb = 25C Full-scale = 6g NL Non Linearity Best fit straight line X, Y axis Full-scale = 2g X, Y axis Vdd = 5V Full-scale = 2g Tamb = 25C @ 5V Logic 0 level Logic 1 level Rout Cload Output impedance Capacitive load drive 320 100 0 2.8 100 0.8 Vdd Vdd/5-10% Vdd/15-10% Vdd/2-10% 1.8 Test Condition Min. 3 1.0 Vdd/2 2.0 6.0 Vdd/5 Vdd/15 0.3 Vdd/5+10% Vdd/15+10% Vdd/2+10% 2.2 Typ. Max. 5.25 Unit V mA V g g V/g V/g %
fuc an Vt Vst
Sensing Element Resonant Frequency Acceleration noise density Self test output voltage Ratiometric to Vdd Self test input
4.0 50
KHz g/ Hz mV V V k pF
1
FUNCTIONALITY
1.1 Sensing element The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase. The equivalent circuit for the sensing element is shown in the below figure; when a linear acceleration is applied, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum variation of the capacitive load is few tenth of pF.
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Figure 1. Equivalent electrical circuit
Cps1
Rs1 S1x Cs1x
Cpr
Rr
Cs2x S2x Cps2 Cps1 Rs2 Rs1 S1y Cs1y Cpr Rr rot
Cs2y S2y Cps2 Rs2
1.2 IC Interface The complete signal processing uses a fully differential structure, while the final stage converts the differential signal into a single-ended one to be compatible with the external world. The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its output to cancel the offset and the 1/f noise. The produced signal is then sent to two different S&Hs, one for each channel, and made available to the outside. The low noise input amplifier operates at 200 kHz while the two S&Hs operate at a sampling frequency of 66 kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output waveform. All the analog parameters (output offset voltage and sensitivity) are ratiometric to the voltage supply. Increasing or decreasing the voltage supply, the sensitivity and the offset will increase or decrease linearly. The feature provides the cancellation of the error related to the voltage supply along an analog to digital conversion chain. 1.3 Factory calibration The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters which are trimmed are: gain, offset, common mode and internal clock frequency. The trimming values are stored inside the device by a poly-fuse structure. Any time the device is turned on, the memorized bits are downloaded into the registers to be employed during the normal operation. The poly-fuse approach allows the final user to utilize the device without any need for further calibration
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LIS2L02AQ
mm DIM. MIN. A A1 b D E e J K L P 5.04 5.04 0.38 0.48 45 REF 1.70 0.19 0.20 0.25 7.0 7.0 0.50 5.24 5.24 0.58 0.198 0.198 0.015 TYP. 1.80 MAX. 1.90 0.21 0.30 MIN. 0.067 0.007 0.008
inch TYP. 0.071 MAX. 0.075 0.008 0.01 0.276 0.276 0.020 0.206 0.206 0.019 45 REF 0.023 0.012
OUTLINE AND MECHANICAL DATA
QFN-44 (7x7x1.8mm) Quad Flat Package No lead
M
G
M
N
34 44 44 1
33
1
DETAIL "N"
23 11
22
12
DETAIL G
SEATING PLANE
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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